The Inter-Integrated Circuit (IIC or I2C) bus and the associated IIC protocol were developed in the 1980s to make it easy to connect electronic systems together. Initially designed for home equipment, this bus protocol has now become a preferred means of configuring complex electronic components.
The IIC protocol can be used to set up communications between a variety of electronic components by means of a bus that conveys only three signals: a data signal SDA containing data and/or addresses to be transmitted, a clock signal SCL setting the rate of the signal SDA, and an electrical reference (ground) signal.
This makes it possible to obtain equipment with very powerful functions (provided with all the power of microprogrammed systems) while keeping a printed circuit board that is very simple as compared with one having a classic circuit diagram.
The IIC protocol defines the succession of possible logic states on the signals SDA and SCL associated with an IIC bus connecting at least two electronic components that have to communicate.
Each electronic component connected to the bus constantly monitors the signals SDA and SCL in order to determine: if the bus is free, if the data transmitted on the bus is addressed for it (in the case of the slave electronic component), and if the data that it transmits is accurately transmitted (in the case of the master electronic component).
To take control of the bus in order to transmit data, the electronic component must initially determine that the bus is at rest. This corresponds to the state where the signals on both the SDA and SCL lines are both logic high (i.e., equal to logic “1”).
After the electronic component verifies that the bus is free, it may take control of the bus: this electronic component then becomes the master and imposes the clock signal SCL. It can then transmit data to one or more slave electronic components connected to the bus. Within the data communications procedure of the IIC bus specification, two unique situations arise which are defined as the IIC start condition and the IIC stop condition.
To transmit one byte of data on the free bus, the master transmits a start condition message on the signal SDA. The IIC start condition occurs when the SDA data signal transitions from a high logic state to a low logic state when the SCL clock signal is logic high. This start condition message indicates that the data will be transmitted. It is followed by a data byte to be transmitted and an enabling bit (where the SDA signal is equal to logic “1”). During this phase, a leading edge of the clock signal SCL enables each bit sent on the signal SDA. The slave (the addressee of the transmitted byte) then imposes a “0” on the signal SDA, thus, informing the master that it has accurately received the transmitted byte. Finally, the master transmits a stop condition signal on the signal SDA, to indicate that the bus will be released. The IIC stop condition occurs when the SDA data signal transitions from a low logic state to a high logic state when the SCL clock signal is logic high.
Reference is now made to FIG. 1 which illustrates the timing of signal transitions on the SCL and SDA lines of the IIC bus in connection with the start condition and the stop condition. The start condition is fulfilled when the following conditions occur: with the signals SDA and SCL initially at logic “1” (bus idle, instant t1), the signal SDA goes to logic “0” (instant t2) while the signal SCL remains at logic “1” for at least a time TDLC after the trailing edge of the signal SDA (instant t3). If necessary, a minimum time may be required between the last leading edge of SCL (instant t1) and the trailing edge of SDA (instant t2) to ensure that the bus is available. The stop condition is fulfilled when the following conditions occur: with the signal SDA initially at logic “0” and the signal SCL initially at logic “1” (instant t4), the signal SDA goes to logic “1” (instant t5) while the signal SCL remains at logic “1” (instant t6). As the case may be, a minimum time may be required between the leading edge of SCL (instant t4) and the leading edge of SDA (instant t5).
To monitor the SDA and SCL signals on the bus, an electronic component connected to the bus may use an interface circuit (for example, an asynchronous digital logic circuit) specifically configured for the detection of the start and stop conditions. This interface circuit may identify the start condition by sampling the level of the clock signal when the falling edge of the data signal is detected. However, glitches on the data line during arbitration in a multi-master environment may erroneously invalidate a previously detected IIC start condition. Furthermore, glitches on the data line while the IIC bus is in an idle state may be erroneously interpreted as an IIC start condition. This, in turn, can lead the interface to lock up and stall the bus.
Additionally, because of potential timing violations generated by SCL/SDA toggles, the included flip-flop circuitry may transition into a meta-stable state resulting in unpredictable flip-flop output signaling. As a consequence, the start and/or stop condition detection circuitry may not work properly. For example, when a new IIC transaction starts, the start condition detection circuitry may not recover immediately for the first data transaction.
To summarize, it is noted that when under a) very noisy conditions on the IIC bus or b) the presence of unpredictable toggling (not IIC start/stop) on the SCL/SDA lines of the IIC bus after the stop condition has been detected, the interface circuitry for start/stop condition detection may not function properly.
Thus, there is a need for an IIC interface circuit that addresses the foregoing and other problems associated with accurately detecting the start condition and stop condition.